FIG. 1 shows a conventional ECL-CMOS level conversion circuit. This circuit is shown in FIG. 3 of, "64K.times.1 BiCMOS ECL RAM with Cross Coupled Level Conversion Circuit" written by T. Shiomi et pages 532-540, The Journal of The Institute of Electronics and Communication Engineers of Japan, vol. J74-C-II, No. 6, June 1991.
The ECL-CMOS level conversion circuit shown in FIG. 1 comprises an input stage 1, a buffer stage 2, an amplifier stage 3, and a driver stage 4. These stages are supplied with a negative operating voltage V.sub.EE and a ground potential. The input stage 1 includes current sources 5 and 6. Buffer stage 2 includes current sources 7 and 8. The input stage 1 includes an input transistor 9, which is a bipolar transistor, and transistors 10 and 11 connected in a differential configuration. A signal input terminal 12 is connected to the base of the input transistor 9. The input terminal 12 receives a signal at an ECL (Emitter-Coupled Logic) level between, e.g., -0.8 V and -1.8 V, from an external ECL IC.
The signal applied to the input terminal 12 is compared with an externally applied constant bias voltage V.sub.BB in the differential amplifier comprising the transistors 10 and 11. Differential outputs developed across load resistors 13 and 14, respectively, are coupled to the bases of bipolar transistors 15 and 16, respectively, of the buffer stage 2. The transistors 15 and 16 decrease the voltage level of the signals at their bases toward V.sub.EE by 1 V.sub.BE (base-emitter voltage), i.e., about 0.7 V, and apply the thus level-shifted signals to PMOS (P-type MOS) transistors 17 and 18 of the amplifier stage 3, respectively.
The amplifier stage 3 includes the PMOS transistors 17 and 18 and a current mirror circuit comprising NMOS (N-type MOS) transistors 19 and 20. The amplifier stage 3 develops an amplified signal in a single-ended form in accordance with the signals applied thereto, and applies the amplified signal to the driver stage 4, which is a BiCMOS driver. The driver stage 4 includes a CMOS circuit comprising a series combination of a PMOS transistor 21 and an NMOS transistor 22 connected between a point of ground potential and a point of V.sub.EE potential, NMOS transistors 24 and 25 connected in series between an output terminal 23 and a point of V.sub.EE potential, and bipolar transistors 26 and 27 connected in series between a point of ground potential and a point of V.sub.EE potential. The output terminal 23 is connected to the junction of the emitter of the bipolar transistor 26 and the collector of the bipolar transistor 27.
The gates of the PMOS transistor 21 and the NMOS transistors 22 and 24 are connected together to the output of the amplifier stage 3. The drains of of the PMOS transistor 21 and the NMOS transistor 22 are connected together and also connected to the base of the transistor 26 and to the gate of the NMOS transistor 25. The base of the transistor 27 is connected to the junction of the NMOS transistors 24 and 25. An output signal developed at the output terminal 23 of the driver stage 4 is used to drive a number of gates within an LSI. The buffer stage 2 is used for preventing signal reflection which could be caused by signal coupling from stray capacitance as well as for providing the previously stated level shift in order to fully turn on the PMOS transistors 17 and 18 of the amplifier stage 3.
Considering, in particular, the buffer stage 2 and the amplifier stage 3 of the conventional BiMOS amplifier device shown in FIG. 1, it is seen that there are as many as four DC current paths between a point of ground potential and a point of V.sub.EE potential. This disadvantageously increases power consumption in these two stages.